Exemplary embodiments of the present invention relate to a semiconductor device fabrication technology, and more particularly, to a semiconductor device and a method for fabricating the same, which can prevent an occurrence of gate-induced drain leakage (GIDL) current and improve drain-induced barrier lowering (DIBL) characteristics.
As the degree of integration of a semiconductor device increases, it becomes more difficult for the semiconductor device to meet the desired operation characteristics thereof. In particular, in the case of a mobile product which calls for higher performance in terms of leakage current characteristics, as the degree of integration of a semiconductor device increases, the thickness of a gate dielectric layer decreases and thus, the occurrence of GIDL current has gradually increased. Also, as a channel length decreases according to the increase in the degree of integration, DIBL characteristics have gradually deteriorated. Hereafter, the above-described concerns in a conventional semiconductor device are illustrated with reference to FIG. 1.
FIG. 1 is a cross-sectional view illustrating a conventional semiconductor device.
Describing a conventional method for fabricating a semiconductor device with reference to FIG. 1, a threshold voltage regulation layer 19 for controlling a threshold voltage is formed on the entire surface of a substrate 11 by an ion implantation process. A gate 15 is formed to have a stack structure in which a gate dielectric layer 12, a gate electrode 13 and a gate hard mask layer 14 are sequentially stacked, and lightly doped drain (LDD) regions 16 are formed in the substrate 11 under both side portions of the gate 15. Spacers 17 are formed on both sidewalls of the gate 15 and junction regions 18 are formed in the substrate 11 on both sides of the gate 15.
The GIDL current is influenced by an electric field created in an area where the gate 15 and the junction regions 18 overlap each other. Therefore, in the conventional art, the occurrence of the GIDL current is suppressed by a method of forming the LDD regions 16, that is, low concentration junction regions having a relatively lower impurity doping concentration than the junction regions 18, in the area where the gate 15 and the junction regions 18 overlap each other.
However, as the degree of integration of a semiconductor device increases, it is difficult to suppress the occurrence of the GIDL current by the method of forming the LDD regions 16, and thus, there are demands for a more fundamental method to suppress the occurrence of the GIDL current.
Under these trends, in order to suppress the occurrence of the GIDL current, techniques developed where the thickness of the gate dielectric layer 12 under both side portions of the gate 15 is set to be greater than the thickness of the gate dielectric layer 12 under the center portion of the gate 15 or where an impurity doping concentration or a work function in the gate electrode 13 is locally controlled. Regardless, these techniques often do not uniformly control the threshold voltage value of the semiconductor device. As a consequence, a concern is caused in that the reliability of the semiconductor device likely deteriorates.
Furthermore, in the conventional semiconductor device, the DIBL characteristics are influenced by a short channel effect (SCE). An ion implantation technique such as halo ion implantation has been used in order to improve the DIBL characteristics.
However, as the degree of integration of a semiconductor device increases and a channel length decreases, it is difficult to improve the DIBL characteristics by the ion implantation technique such as halo ion implantation, and thus, another approach to address above discussed concerns may be useful.
Furthermore, as the degree of integration of a semiconductor device increases, if the impurity doping concentration of the threshold voltage regulation layer 19 is increased so as to control a threshold voltage, the operation characteristics of the semiconductor device may further deteriorate due to the occurrence of the GIDL current and the deterioration of the DIBL characteristics.